送信

連続受信プログラムに送信部を追加してみます。この部分はとにかく送信だけはしますが、今のところ有為なデータを送るわけではありません。まずは形からです。

大幅に変更したのはsetupSport()とsetupTCB()です。この二つはこれまでの受信部の設定に加えて送信部の設定が加わりました。送信といっても受信と同じデータ形式を送るだけですから、同じサイズのバッファを同じようなTCB構成でとりあつかうだけです。従って、追加されたコードはほとんど受信部とかわりません。注意すべき点はsetupTCB()の中のconfiguration設定で、送信部はTRANビットをセットしていません。これはTRANビットがメモリーへの書き込みの場合のみ1にするビットだからです。

#include <def2191.h>
#include "def2191bit.h"
#include <sysreg.h>
#include <signal.h>

#define BUFSIZE 6

struct TDMADescriptor 
{
        int configuration, startPage, startAddress, count;
        struct TDMADescriptor * nextDescriptor;
};

int rxBuffer[BUFSIZE*2], txBuffer[BUFSIZE*2];
struct TDMADescriptor  rxTCB1, rxTCB2, txTCB1, txTCB2;

void sportRxHandler( int sig );
void sportTxHandler( int sig );
void setupSport( void );
void setupTCB( void );
void reset1885( void );

int main(void)
{
        reset1885( );
        interrupt( SIG_INT5, sportRxHandler );          // SIG_INT5 is default interupt for SPORT0 RX
        interrupt( SIG_INT6, sportTxHandler );          // SIG_INT6 is default interupt for SPORT0 RX
        enable_interrupts();                            // グローバル割り込みイネーブル
        setupTCB();                                                                     // TCB Configuratoin
        setupSport();                                                           // SPORT0 Configuration
        while ( 1 )
                ;
}

void setupSport( void )
{

        sysreg_write( sysreg_IOPG, SPORT0_Controller_Page );

                // Disabling
        io_space_write( SP0DR_CFG, 0 );         // RX DMA Disable
        io_space_write( SP0DT_CFG, 0 );         // TX DMA Disable
        io_space_write( SP0_RCR, 0 );           // RX disable
        io_space_write( SP0_TCR, 0 );           // TX disable

                        // RX setting.
        io_space_write( SP0_RFSDIV, 255 );              // 256 bit per frame
        io_space_write( SP0_MRCS0, 0x003f );    // only 6 channel
        io_space_write( SP0_MRCS1, 0 ); 
        io_space_write( SP0_MRCS2, 0 ); 
        io_space_write( SP0_MRCS3, 0 ); 
        io_space_write( SP0_MRCS4, 0 ); 
        io_space_write( SP0_MRCS5, 0 ); 
        io_space_write( SP0_MRCS6, 0 ); 
        io_space_write( SP0_MRCS7, 0 ); 

        io_space_write( SP0DR_CP, (int) &rxTCB1 );      // set chain pointer
        io_space_write( SP0DR_CPR, 1 );         // ready descriptor pointer
        io_space_write( SP0DR_CFG, DEN );

                        // TX setting
        io_space_write( SP0_TFSDIV, 255 );              // 256 bit per frame
        io_space_write( SP0_MTCS0, 0x003f );    // only 6 channel
        io_space_write( SP0_MTCS1, 0 ); 
        io_space_write( SP0_MTCS2, 0 ); 
        io_space_write( SP0_MTCS3, 0 ); 
        io_space_write( SP0_MTCS4, 0 ); 
        io_space_write( SP0_MTCS5, 0 ); 
        io_space_write( SP0_MTCS6, 0 ); 
        io_space_write( SP0_MTCS7, 0 ); 

        io_space_write( SP0DT_CP, (int) &txTCB1 );      // set chain pointer
        io_space_write( SP0DT_CPR, 1 );         // ready descriptor pointer
        io_space_write( SP0DT_CFG, DEN );

                // start operation.
        io_space_write( SP0_MCMC1, 0 << WOFF_OFST | 1 << WSIZE_OFST | 1 << MFD_OFST | MCM );
        io_space_write( SP0_MCMC2, MCDRXPE | MCDTXPE );
        io_space_write( SP0_RCR,  IRFS | SLEN_16 | RSPEN );
        io_space_write( SP0_TCR,  IRFS | SLEN_16 | TSPEN );
}

void setupTCB( void )
{
                        // setting up the DMA TCB1
        rxTCB1.configuration = DOWN | DCOME | TRAN | DEN;
        rxTCB1.startPage = 0;
        rxTCB1.startAddress = (int)rxBuffer;
        rxTCB1.count = BUFSIZE;
        rxTCB1.nextDescriptor = &rxTCB2;
                        // setting up the DMA TCB2
        rxTCB2.configuration = DOWN | DCOME | TRAN | DEN;
        rxTCB2.startPage = 0;
        rxTCB2.startAddress = (int)&rxBuffer[BUFSIZE];
        rxTCB2.count = BUFSIZE;
        rxTCB2.nextDescriptor = &rxTCB1;

                                // setting up the DMA TCB1
        txTCB1.configuration = DOWN | DCOME | DEN;
        txTCB1.startPage = 0;
        txTCB1.startAddress = (int)txBuffer;
        txTCB1.count = BUFSIZE;
        txTCB1.nextDescriptor = &txTCB2;
                        // setting up the DMA TCB2
        txTCB2.configuration = DOWN | DCOME | DEN;
        txTCB2.startPage = 0;
        txTCB2.startAddress = (int)&txBuffer[BUFSIZE];
        txTCB2.count = BUFSIZE;
        txTCB2.nextDescriptor = &txTCB1;
}

int count = 0;
void sportRxHandler( int sig )
{

        sysreg_write( sysreg_IOPG, SPORT0_Controller_Page );
        io_space_write( SP0DR_IRQ, 1 );         // clear interrupt from SP0 RX

        if ( !( rxTCB1.configuration & DOWN ) ) // Descriptor2 Finish?
                rxTCB1.configuration |= DOWN;   // give ownership of TCB1 to DMA engine.
        else
                rxTCB2.configuration |= DOWN;   // give ownership of TCB2 to DMA engine.

}

void sportTxHandler( int sig )
{

        sysreg_write( sysreg_IOPG, SPORT0_Controller_Page );
        io_space_write( SP0DT_IRQ, 1 );         // clear interrupt from SP0 TX

        if ( !( txTCB1.configuration & DOWN ) ) // Descriptor2 Finish?
                txTCB1.configuration |= DOWN;   // give ownership of TCB1 to DMA engine.
        else
                txTCB2.configuration |= DOWN;   // give ownership of TCB2 to DMA engine.

        count ++;
}
void reset1885( void )
{
                int curDIR, curIOPG, i;
        
                curIOPG = sysreg_read( sysreg_IOPG );
                sysreg_write( sysreg_IOPG, General_Purpose_IO );
                curDIR = io_space_read( DIR );                  // get the current Direction Setting
                io_space_write( DIR, curDIR | 0x0080 );         // set PF7 output ( AD1885 /reset )
                io_space_write( FLAGC, 0x0080 );                // asseart /reset_ad1885
                for ( i=0; i<160; i++ )
                        asm volatile( "nop;" );
                io_space_write( FLAGS, 0x0080 );                // asseart /reset_ad1885
                sysreg_write( sysreg_IOPG, curIOPG );
}

⇒次はめんどくさい